Moisture Measurements in PCBs and Impact of Design on Desorption Behaviour

High levels of residual moisture in PCBs are problematic and can result in delamination during soldering and rework. Moisture accumulates during storage and industry practice recommends specific levels of baking to avoid delamination. This paper will discuss the use of capacitance measurements to follow the absorption and desorption behaviour of moisture. The PCB design used in this work, focused on the issue of baking out moisture trapped between copper planes. The PCB was designed with different densities of plated through holes and drilled holes in external copper planes, with capacitance sensors located on the inner layers. For trapped volumes between copper planes, the distance between holes proved to be critical in affecting the desorption rate. For fully saturated PCBs, the desorption time at elevated temperatures was observed to be in the order of hundreds of hours. Finite difference diffusion modelling was carried out for moisture desorption behaviour for plated through holes and drilled holes in copper planes. A meshed copper plane was also modelled evaluating its effectiveness for assisting moisture removal and decreasing bake times. Results also showed, that in certain circumstances, regions of the PCB under copper planes initially increase in moisture during baking. Introduction Delamination during soldering can occur due to high levels of moisture within a PCB, which rapidly expands during soldering and rework operations. This delamination may not always be visible as a raised or discoloured surface. Whilst techniques such as pulsed thermography [1] and acoustic microscopy can be used to detect delamination and prevent delaminated boards from entering service, it is preferable to avoid delamination completely through suitable board storage, design and pre-baking. Moisture enters the PCB when the partial pressure of the moisture in the atmosphere is greater externally to that inside the PCB. The random thermal agitation of the water molecules causes them to diffuse to regions of lower moisture concentration further into the PCB. The diffusion of moisture in PCBs has previously been modelled using various techniques [2-4] and Weide-Zaage et al [5] have considered different arrangements of internal copper layers. To prevent delamination in the soldering phase, IPC guidelines suggest keeping the moisture content to less than 0.1% by weight for high (260°C) temperature soldering and less than 0.2% for low temperature (230°C) soldering [6]. Moisture content can be experimentally assessed through mass measurements of the PCB, although the percentage change in mass will be dependent on the amount of copper on the board. Prior work investigating moisture uptake in PCB’s has identified capacitance measurements as being capable of detecting changes in moisture content [7]. Capacitance measurements are able to detect moisture content changes, as they are dependent on the permittivity (which is dependent on moisture) of the material between the electrodes. Whilst mass measurements reflect the average moisture condition of a board, capacitance sensors can be positioned to measure the moisture content locally. Moisture uptake and removal at three bake temperatures was also modelled and fitting of the data yielded diffusion coefficients for the FR-4 composite material [8]. These coefficients have been used here to model the diffusion of moisture into PCBs with features similar to that experimentally investigated. Experimental A test board has been designed with capacitors situated on inner layers between external copper planes (Figure 1). The board had four sections, each comprising a grid of 3 by 3 capacitors (20 mm by 20 mm in size), with different plated and non-plated hole densities. The different hole densities corresponded to centre-to-centre spacings of 4, 5.6 and 8 mm, as well as a section with uninterrupted copper planes. Versions of this board were built, with either plated through holes (PTH) or non-PTHs. The boards were of 4 layer design using 7628 prepreg (pre-impregnated composite fibres) either side of a 1 mm copper clad core. The 7628 prepreg had a resin content of 51±3%, fibre thickness of 0.173 mm and fabric count (warp x fill) of 17.3×12.2 per cm. The capacitance was measured across the central layers, which were 1 mm apart. PTHs were 0.4 mm drilled size with a land diameter of 0.8 mm. The clearance distance to the copper plane was a further 0.2 mm. Non-PTHs were drilled at 0.8 mm diameter to maintain a constant clearance to the copper plane. The design of the grid capacitors is shown in Figure 2, the grids consisting of 0.2 mm tracks on a pitch of 0.8 mm with 25 openings (2.4 x 2.4 mm) available for holes. The test boards were initially soaked in an 85% RH/85°C environment for two months. Subsequently, the boards were divided into three groups in order to investigate moisture removal at bake temperatures of 80, 110 and 125°C. The boards were periodically removed from the ovens and allowed to cool for 45 minutes; the capacitance values were then measured As originally published in the IPC Printed Circuit Expo, APEX & Designer Summit Proceedings.